#ifndef __CAN_FUNC_C__
#define __CAN_FUNC_C__

#include "can_var.c"


//Initial can, set bustiming 0/1 & choose basic mode & set acceptance code

void test_info(char * str)
{
	char i;

	i = 0;
	while(*(str+i)!='\0')
	{
	 	*info = *(str+i);
		i++;
	}
	*info = '\n';
}

void InitCan_Basic(char bustiming0, char bustiming1, char accep_code,char accep_mask)
{
	 EO = 0;					//SET CAN 0;
	 CAN_BASIC_CONTROL = 0x01;	//SET RESET MODE
	// CAN_BUSTIMING0 = 0x43;		//sjw = 01b; BRP = 000011b
	// CAN_BUSTIMING1 = 0x2F;		//sam = 0(sigle sample)
	 CAN_BUSTIMING0 = bustiming0;
	 CAN_BUSTIMING1 = bustiming1;
	 CAN_CLOCK_DIVIDER = 0x00;	//choose basic mode;
	 CAN_BASIC_ACCEP_CODE = accep_code;
	 CAN_BASIC_ACCEP_MASK = accep_mask;
}

//Initial can, set bustiming 0/1 & choose basic mode & set acceptance code
void InitCan2_Basic(char bustiming0, char bustiming1, char accep_code,char accep_mask)
{
	 EO = 0x80;					//SET CAN 0;
	 CAN_BASIC_CONTROL = 0x01;	//SET RESET MODE
	// CAN_BUSTIMING0 = 0x43;		//sjw = 01b; BRP = 000011b
	// CAN_BUSTIMING1 = 0x2F;		//sam = 0(sigle sample)
	 CAN_BUSTIMING0 = bustiming0;
	 CAN_BUSTIMING1 = bustiming1;
	 CAN_CLOCK_DIVIDER = 0x00;	//choose basic mode;
	 CAN_BASIC_ACCEP_CODE = accep_code;
	 CAN_BASIC_ACCEP_MASK = accep_mask;
}

//send a basic frame. used in non-irq functions.
void can_basic_send(char accep_code, char * data_ptr, char data_length)
{
 	EO = 0;
	CAN_TRANS_ID1 = accep_code;
	CAN_TRANS_ID2 = data_length;	//id2~id1 set to 0; rtr = 0; DLC is data_length <= 8

	CAN_TRANS_DATA1 = *data_ptr++;
	CAN_TRANS_DATA2 = *data_ptr++;
	CAN_TRANS_DATA3 = *data_ptr++;
	CAN_TRANS_DATA4 = *data_ptr++;
	CAN_TRANS_DATA5 = *data_ptr++;
	CAN_TRANS_DATA6 = *data_ptr++;
	CAN_TRANS_DATA7 = *data_ptr++;	
	CAN_TRANS_DATA8 = *data_ptr++;

	CAN_BASIC_COMMAND = 0x01;		//transfer request;

}

//send a basic frame. used in non-irq functions.
void can2_basic_send(char accep_code, char * data_ptr, char data_length)
{
 	EO = 0x80;
	CAN_TRANS_ID1 = accep_code;
	CAN_TRANS_ID2 = data_length;	//id2~id1 set to 0; rtr = 0; DLC is data_length <= 8

	CAN_TRANS_DATA1 = *data_ptr++;
	CAN_TRANS_DATA2 = *data_ptr++;
	CAN_TRANS_DATA3 = *data_ptr++;
	CAN_TRANS_DATA4 = *data_ptr++;
	CAN_TRANS_DATA5 = *data_ptr++;
	CAN_TRANS_DATA6 = *data_ptr++;
	CAN_TRANS_DATA7 = *data_ptr++;	
	CAN_TRANS_DATA8 = *data_ptr++;

	CAN_BASIC_COMMAND = 0x01;		//transfer request;
}

//read rx_buffer to ExRAM. used in no-irq functions.
void can_basic_receive()
{
	char string[8]="C1POLLRE";			   //write interrupt information in external memory
	int i;
	char temp;
	char temp_data[8];

	for(i=0;i<8;i++)
	{
	 	*info++ = string[i];
	}

	EO = 0x00;
	temp = CAN_RECEIVE_ID2;
	temp &= 0x0F;
	if(temp > 8) temp = 8;		//read the length of data
	temp_data[0] = CAN_RECEIVE_DATA1;
	temp_data[1] = CAN_RECEIVE_DATA2;
	temp_data[2] = CAN_RECEIVE_DATA3;		
	temp_data[3] = CAN_RECEIVE_DATA4;
	temp_data[4] = CAN_RECEIVE_DATA5;
	temp_data[5] = CAN_RECEIVE_DATA6;
	temp_data[6] = CAN_RECEIVE_DATA7;
	temp_data[7] = CAN_RECEIVE_DATA8;
	for(i=0;i<temp;i++)
	{
	 	*received_data++ = temp_data[i];
	}
}

//read rx_buffer to ExRAM. used in no-irq functions.
void can2_basic_receive()
{
	char string[8]="C2POLLRE";			   //write interrupt information in external memory
	int i;
	char temp;
	char temp_data[8];

	EO = 0x80;
	for(i=0;i<8;i++)
	{
	 	*info++ = string[i];
	}
	temp = CAN_RECEIVE_ID2;
	temp &= 0x0F;
	if(temp > 8) temp = 8;		//read the length of data
	temp_data[0] = CAN_RECEIVE_DATA1;
	temp_data[1] = CAN_RECEIVE_DATA2;
	temp_data[2] = CAN_RECEIVE_DATA3;		
	temp_data[3] = CAN_RECEIVE_DATA4;
	temp_data[4] = CAN_RECEIVE_DATA5;
	temp_data[5] = CAN_RECEIVE_DATA6;
	temp_data[6] = CAN_RECEIVE_DATA7;
	temp_data[7] = CAN_RECEIVE_DATA8;
	for(i=0;i<temp;i++)
	{
	 	*received_data++ = temp_data[i];
	}
}

//release rx buffer command. used in no-irq functions.
void can_basic_release_buffer()
{
	EO = 0x00;
	CAN_BASIC_COMMAND = 0x04;		//release rx buffer 0000_0100;
}

//release rx buffer command. used in no-irq functions.
void can2_basic_release_buffer()
{
	EO = 0x80;
	CAN_BASIC_COMMAND = 0x04;		//release rx buffer 0000_0100;
}

//polling trans/receive test   (test IR reg: when interrupt disable, read should be 0xE0)
void can_basic_polling_test()
{
	char xdata * data_ptr;
	data_ptr = send_data;			//the address of data need to be sent
	received_data = 300;	//receive data storge at 0x300 in ex_ram
////////////////////////polling trans & receive test///////////////////////////////

//////////////////////////////can 1 send and can 2 receive ////////////////////////////////
	 EO = 0;
	 CAN_BASIC_CONTROL = 0x00;	//all interrupt disable, exit reset mode
	 EO = 0x80;
	 CAN_BASIC_CONTROL = 0x00;	//All interrupt disable, exit reset mode

	 //frame 1 
	 can_basic_send(0xAB,data_ptr,1);	//send 1 byte
	 data_ptr += 1;
	 EO = 0x00;
	 
	 //frame 2
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = CAN_BASIC_INTERRUPT;	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,2);	//send 2 byte
	 data_ptr += 2;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	 //frame 3
	 EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,3);	//send 3 byte
	 data_ptr += 3;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	 //frame 4
	 EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,4);	//send 4 byte
	 data_ptr += 4;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();
 	 
	//frame 5
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,5);	//send 5 byte
	 data_ptr += 5;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 6
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,6);	//send 6 byte
	 data_ptr += 6;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 7
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,7);	//send 7 byte
	 data_ptr += 7;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 8
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,8);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 9
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,9);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 10
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,10);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 11
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,11);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 12
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,12);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 13
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,13);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 14
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,14);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//frame 15
	EO = 0x00;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_send(0xAB,data_ptr,15);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x80;	//receive frame 14
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	 EO = 0x80;	//receive frame 15
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_receive();
	 can2_basic_release_buffer();

	//////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp != 92)
	 	P0 = 'N';				//test failed;
	  
//////////////////////////can 2 send and can 1 receive ///////////////////////////////////////

	 received_data = 300;	//receive data storge at 0x300 in ex_ram
	 data_ptr = send_data;			//the address of data need to be sent
	 //frame 1 
	 can2_basic_send(0xAB,data_ptr,1);	//send 1 byte
	 data_ptr += 1;
	 EO = 0x80;
	 
	 //frame 2
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_send(0xAB,data_ptr,2);	//send 2 byte
	 data_ptr += 2;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_release_buffer();

	 //frame 3
	 EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can2_basic_send(0xAB,data_ptr,3);	//send 3 byte
	 data_ptr += 3;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	 //frame 4
	 EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,4);	//send 4 byte
	 data_ptr += 4;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();
 	 
	//frame 5
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,5);	//send 5 byte
	 data_ptr += 5;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 6
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,6);	//send 6 byte
	 data_ptr += 6;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 7
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,7);	//send 7 byte
	 data_ptr += 7;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 8
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,8);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 if( CAN_BASIC_INTERRUPT != 0x00) P0 = 'N';	//when interrupt disable, IR should be 0x00 
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 9
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,9);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 10
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,10);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 11
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,11);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 12
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,12);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 13
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,13);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 14
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,14);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//frame 15
	EO = 0x80;
	 while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty
	 can2_basic_send(0xAB,data_ptr,15);	//send 8 byte
	 data_ptr += 8;
	 
	 EO = 0x00;	//receive frame 14
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	 EO = 0x00;	//receive frame 15
	 while((~CAN_BASIC_STATUS) & 0x01);   //can 2 recieve buffer ready
	 can_basic_receive();
	 can_basic_release_buffer();

	//////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp == 92)
	 	P0 = 'Y';				//test successful;
	 else
	 	P0 = 'N';
}

//trans & receive by irq test
void can_basic_irq_test()
{
////////////////interrupt trans & receive test/////////////////////
	 EO = 0;
	 CAN_BASIC_CONTROL = 0x1E;//overflow enable, error enable, transfer enable, receive enable;
	 EO = 0x80;
	 CAN_BASIC_CONTROL = 0x1E;//overflow enable, error enable, transfer enable, receive enable;
	 
	 accep_code_global = 0xAB; //set accep_code will be sent in irq
	 trans_data_ptr_irq = send_data; //data pointer used in irq
	 received_data = 300;		//set receive data address.
	 counter_global = 2;	   //data length.
	 counter_global_2 = 0;		//data have been receive.

	 can_basic_send(0xAB,trans_data_ptr_irq,1);
	 trans_data_ptr_irq ++;
	 
	 while(counter_global_2 != 15);	   //have receive 15 frames
	 
	 //////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp != 92)
	 	P0 = 'N';				//test successful;

	 //////can2 SEND CAN 1 receive
	 trans_data_ptr_irq = send_data; //data pointer used in irq
	 received_data = 300;		//set receive data address.
	 counter_global = 2;	   //data length.
	 counter_global_2 = 0;		//data have been receive.

	 can2_basic_send(0xAB,trans_data_ptr_irq,1);
	 trans_data_ptr_irq ++;

	 while(counter_global_2 != 15);	   //have receive 15 frames

	 //////start check receive value/////
	 trans_temp = 0x0000;
	 recei_temp = 300;	//ptr point at the beginning of the receive data.
	 while ( *recei_temp == *trans_temp)
	 {
	 	if(trans_temp == 92) break;	   //(1+2+3+4+5+6+7+8+8+8+8+8+8+8+8)
		recei_temp ++;
		trans_temp ++;
	 }
	 if(trans_temp == 92)
	 	P0 = 'Y';				//test successful;
	 else
	 	P0 = 'N';
}

//send wrong ID test.
void can_basic_id_test()
{
	//////////////////send wrong ID test/////////////////////	
	EO = 0;
	CAN_BASIC_CONTROL = 0x00;	//all interrupt disable, exit reset mode
	EO = 0x80;
	CAN_BASIC_CONTROL = 0x00;	//All interrupt disable, exit reset mode
	
	/////CAN 1 SEND CAN 2 RECEIVE/////
	can_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x00;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;

	EO = 0x80; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //frame 2 should be received, frame 1 lost.
	
	// frame 1 lost ,frame 2 received, so there should be only 1 data in buffer and it's '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		test_info("fail_id test_wrong id test_1-2");
		P0 = 'N';
	}
	/////CAN 2 send CAN 1 RECEIVE /////
	can2_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x80;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can2_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;
	EO = 0x00; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //frame 2 should be received, frame 1 lost.
	// frame 1 lost ,frame 2 received, so there should be only 1 data in buffer and it's '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		P0 = 'N' ;
		test_info("fail_id test_wrong id test_2-1");
	}
	else
	{
		P0 = 'Y';
		test_info("OK_id test_wrong id test");
	}

	/////////////////accecptance mask disable test///////////////
	// change mask to 11111111 (all bits irrelevant)
 	EO = 0;					//SET CAN 0;
	 CAN_BASIC_CONTROL = 0x01;	//SET RESET MODE
	 CAN_BASIC_ACCEP_MASK = 0xFF; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00;	//exit reset mode
	EO = 0x80;
	 CAN_BASIC_CONTROL = 0x01; //SET RESET MODE
	 CAN_BASIC_ACCEP_MASK = 0xFF; //mask set to all irrelevant
	 CAN_BASIC_CONTROL = 0x00; 	//exit reset mode

	 /////CAN 1 SEND CAN 2 RECEIVE/////
	can_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x00;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;

	EO = 0x80; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //both frame 1 & 2 should received.
	
	//buffer should exsit 2 bytes data : '1', '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '1'))
	{
		P0 = 'N' ;
		test_info("fail_id test_id mask test_1-2_p1");
	}
	can2_basic_release_buffer();
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		P0 = 'N' ;
		test_info("fail_id test_id mask test_1-2_p2");
	}

	/////CAN 2 send CAN 1 RECEIVE /////
	can2_basic_send(0xAA,send_data,1);	 //send frame 1, data is '1'; but id is wrong.
	EO = 0x80;
	while( (~CAN_BASIC_STATUS) & 0x04);	 //can 1 tx buffer empty

	can2_basic_send(0xAB,send_data+1,1);	//send frame 2, data is '2'; id is right;
	EO = 0x00; 
	while( (~CAN_BASIC_STATUS) & 0x01);	 //both frame 1 & 2 received
	
	//buffer should exsit 2 bytes data : '1', '2'
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '1'))
	{
		P0 = 'N' ;
		test_info("fail_id test_id mask test_2-1_p1");
	}
	can_basic_release_buffer();
	if((CAN_RECEIVE_ID2 != 0x01) || (CAN_RECEIVE_DATA1 != '2'))
	{
		P0 = 'N' ;
		test_info("fail_id test_id mask test_2-1_p2");
	}
	else	
	{
		P0 = 'Y' ;
		test_info("OK_id test_id mask test_2-1");
	}

} 




#endif
